ESys.net is a hardware system design library for the .net/Mono frameworks that is basically a port of the SystemC framework for C++.
On the other hand, it offers a greater range of expression, similar to object-oriented design partitioning and template classes.
SystemC |
SystemC provides signed and unsigned fixed point data types.
SystemC is an example of such—embedded system hardware can be modeled as non-detailed architectural blocks (blackboxes with modeled signal inputs and output drivers).
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Companies such as Cadence, Synopsys and Agility Design Solutions are promoting SystemC as a way to combine high level languages with concurrency models to allow faster design cycles for FPGAs than is possible using traditional HDLs.
The first approach ultimately resulted in SystemVerilog and extensions to VHDL while the second resulted in SystemC, all of which became Institute of Electrical and Electronics Engineers (IEEE) standards for the semiconductor industry.