In the mapping of virtual memory addresses, instead of needing an MMU, the MCP systems are descriptor-based.
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Some operating systems, such as OpenBSD with its W^X feature, and Linux with the Exec Shield or PaX patches, may also limit the length of the code segment, as specified by the CS register, to disallow execution of code in modifiable regions of the address space.
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The W^X, Exec Shield, and PaX mechanisms described above emulate per-page non-execute support on machines x86 processors lacking the NX bit by setting the length of the code segment, with a performance loss and a reduction in the available address space.
Central processing unit | Law & Order: Special Victims Unit | Management | The Unit | Federal Emergency Management Agency | Bureau of Land Management | MIT Sloan School of Management | memory | management | Read-only memory | Larissa (regional unit) | Digital rights management | International Institute for Management Development | Economist Intelligence Unit | Diesel multiple unit | Simple Network Management Protocol | central processing unit | Office of Management and Budget | Object Management Group | Company (military unit) | UNIT | unit | Singapore Management University | Kellogg School of Management | Chania (regional unit) | mya (unit) | Indian Institutes of Management | Indian Institute of Management Ahmedabad | diesel multiple unit | Customer relationship management |
Includes keyboard controller, UART, parallel interface, MMU, watchdog timer and PMU.
With the memory management unit, MicroBlaze is capable of hosting operating systems requiring hardware-based paging and protection, such as the Linux kernel.
It required a memory management unit (MMU) to support memory protection, so was not compatible with 8086 and 8088 processors.
Zilog added a memory management unit (MMU) to expand the addressing range to 16 MB, features for multitasking and multiprocessor and coprocessor configurations, a 256 byte cache, and a huge number of new instructions and addressing modes (giving a total of over 2000 combinations).
Graphics address remapping table, a memory management unit used in computer graphics cards