There was considerable delay (possibly procrastination) between the first Verilog-A language reference manual and the full Verilog-AMS, and in that time Verilog moved to the IEEE, leaving Verilog-AMS behind at Accellera.
Verilog |
Integrated device manufacturers (IDM) receive the ARM Processor IP as synthesizable RTL (written in Verilog).
The objective of the meeting was to define requirements for a next-generation design language that would address perceived shortcomings in existing languages such as VHDL and Verilog.
It allows behavioral Verilog code to invoke C functions, and C functions to invoke standard Verilog system tasks.